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? semiconductor components industries, llc, 2016 july, 2016 ? rev. 4 1 publication order number: ar0135cs/d ar0135cs 1/3\inch 1.2 mp cmos digital image sensor with global shutter description the ar0135cs from on semiconductor is a 1/3-inch 1.2 mp cmos digital image sensor with an active-pixel array of 1280 (h) 960 (v). it is designed for low light performance and features a global shutter for accurate capture of moving scenes and synchronization with pulsed light sources. it includes sophisticated camera functions such as auto exposure control, windowing, scaling, row skip mode, and both video and single frame modes. it is programmable through a simple tw o-wire serial interface. the ar0135cs produces extraordinarily clear, sharp images, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of applications, including scanning and machine vision. table 1. key performance parameters parameter typical value optical format 1/3-inch (6 mm) active pixels 1280 (h) 960 (v) = 1.2 mp pixel size 3.75 m color filter array rgb bayer, monochrome cra 0 , 25 shutter type global shutter input clock range 6?50 mhz output pixel clock (maximum) 74.25 mhz output serial parallel hispi 12-bit frame rate full resolution 720p 54 fps 60 fps responsivity (under d65 with 670 nm ircf) rgb bayer monochrome 34 ke ? /lux*sec 85 ke ? /lux*sec snr max 40.7 db dynamic range 71.1 db supply voltage i/o digital analog hispi 1.8 or 2.8 v 1.8 v 2.8 v 0.4 v power consumption < 400 mw operating temperature ?30 c to + 70 c (ambient) ?30 c to + 80 c (junction) package options 9 9 mm 63-pin ibga bare die www.onsemi.com f eatures ? on semiconductor?s next generation global shutter technology ? superior low-light performance ? hd video (720p60) ? video/single frame mode ? flexible row-skip modes ? on-chip ae and statistics engine ? parallel and serial output ? support for external led or flash ? auto black level calibration ? context switching a pplications ? barcode scanner ? 3d scanning ? positional tracking ? iris scanning ? augmented reality ? virtual reality ? biometrics ? machine vision ? gesture control see detailed ordering and shipping information on page 2 o f this data sheet. ordering information ibga63 9 9 case 503az
ar0135cs www.onsemi.com 2 ordering information table 2. orderable part numbers part number description orderable product attribute description ar0135cs2m00sud20 mono, 0 cra, bare die ar0135cs2m00suea0?dpbr mono, 0 cra, ibga dry pack with protective film, double side bbar glass ar0135cs2m00suea0?dpbr1 mono, 0 cra, ibga dry pack with protective film, double side bbar glass, mpq = 260 ar0135cs2m00suea0?drbr mono, 0 cra, ibga dry pack without protective film, double side bbar glass ar0135cs2m00suea0?drbr1 mono, 0 cra, ibga dry pack without protective film, double side bbar glass, mpq = 260 ar0135cs2m00suea0?tpbr mono, 0 cra, ibga tape & reel with protective film, double side bbar glass ar0135cs2m00suea0?trbr mono, 0 cra, ibga tape & reel without protective film, double side bbar glass ar0135cs2m00sueah3?gevb mono, 0 cra, head board ar0135cs2m25sud20 mono, 25 cra, die ar0135cs2m25suea0?dpbr mono, 25 cra, ibga dry pack with protective film, double side bbar glass ar0135cs2m25suea0?dpbr1 mono, 25 cra, ibga dry pack with protective film, double side bbar glass, mpq = 260 ar0135cs2m25suea0?drbr mono, 25 cra, ibga dry pack without protective film, double side bbar glass ar0135cs2m25suea0?drbr1 mono, 25 cra, ibga dry pack without protective film, double side bbar glass, mpq = 260 ar0135cs2m25suea0?tpbr mono, 25 cra, ibga tape & reel with protective film, double side bbar glass ar0135cs2m25suea0?trbr mono, 25 cra, ibga tape & reel without protective film, double side bbar glass ar0135cs2m25sueah3?gevb mono, 25 cra, head board ar0135cs2c00sud20 color, 0 cra, die ar0135cs2c00suea0?dpbr color, 0 cra, ibga dry pack with protective film, double side bbar glass ar0135cs2c00suea0?dpbr1 color, 0 cra, ibga dry pack with protective film, double side bbar glass, mpq = 260 ar0135cs2c00suea0?drbr color, 0 cra, ibga dry pack without protective film, double side bbar glass ar0135cs2c00suea0?drbr1 color, 0 cra, ibga dry pack without protective film, double side bbar glass, mpq = 260 ar0135cs2c00suea0?tpbr color, 0 cra, ibga tape and reel with protective film, double side bbar glass ar0135cs2c00suea0?trbr color, 0 cra, ibga tape and reel without protective film, double side bbar glass ar0135cs2c00sueah3?gevb color, 0 cra, head board general description the ar0135cs from on semiconductor can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. the default mode output is a full-resolution image at 54 frames per second (fps). it outputs 12-bit raw data, using either the parallel or serial (hispi) output ports. the device may be operated in video (master) mode or in frame trigger mode. frame_valid and line_valid signals are output on dedicated pins, along with a synchronized pixel clock. a dedicated flash pin can be programmed to control external led or flash exposure illumination. the ar0135cs includes additional features to allow application-specific tuning: windowing, adjustable auto- exposure control, auto black level correction, on-board temperature sensor, and row skip and digital binning modes. the sensor is designed to operate in a wide temperature range (?30 c to +80 c).
ar0135cs www.onsemi.com 3 functional overview the ar0135cs is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. it uses an on-chip, phase-locked loop (pll) that can be optionally enabled to generate all internal clocks from a single master input clock ru nning between 6 and 50 mhz. the maximum output pixel rate is 74.25 mp/s, corresponding to a clock rate of 74.25 mhz. f igure 1 shows a block diagram of the sensor. figure 1. block diagram control registers analog processing and a/d conversion active pixel sensor (aps) array pixel data path (signal processing) timing and control (sequencer) auto exposure and stats engine temperature sensor otpm memory pll external clock signal output parallel output flash trigger two-wire serial interface power user interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. the core of the sensor is a 1.2 mp active-pixel sensor array. the ar0135cs features global shutter technology for accurate capture of moving images. the exposure of the entire array is controlled by programming the integration time by register setting. all rows simultaneously integrate light prior to readout. once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an analog-to-digital converter (adc). the output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). the pixel data are output at a rate of up to 74.25 mp/s, in parallel to frame and line synchronization signals. features overview the ar0135cs global sensor shutter has a wide array of features to enhance functionality and to increase versatility. a summary of features follows. please refer to the ar0135cs developer guide for detailed feature descriptions, register settings, and tuning guidelines and recommendations. ? operating modes the ar0135cs works in master (video), trigger (single frame), or auto trigger modes. in master mode, the sensor generates the integration and readout timing. in trigger mode, it accepts an external trigger to start exposure, then generates the exposure and readout timing. the exposure time is programmed through the two-wire serial interface for both modes. trigger mode is not compatible with the hispi interface. ? window control configurable window size and blanking times allow a wide range of resolutions and frame rates. digital binning and skipping modes are supported, as are vertical and horizontal mirror operations. ? context switching context switching may be used to rapidly switch between two sets of register values. refer to the ar0135cs developer guide for a complete set of context switchable registers. ? gain the ar0135cs global shutter sensor can be configured for analog gain of up to 8x, and digital gain of up to 8x. ? automatic exposure control the integrated automatic exposure control may be used to ensure optimal settings of exposure and gain are computed and updated every other frame. refer to the ar0135cs developer guide for more details. ? hispi the ar0135cs global shutter image sensor supports two or three lanes of packetized-sp protocols of on semiconductor?s high-speed serial pixel interface. ? pll an on chip pll provides reference clock flexibility and supports spread spectrum sources for improved emi performance.
ar0135cs www.onsemi.com 4 ? reset the ar0135cs may be reset by a register write, or by a dedicated input pin. ? output enable the ar0135cs output pins may be tri-stated using a dedicated output enable pin. ? temperature sensor the temperature sensor is only guaranteed to be functional when the ar0135cs is initially powered-up or is reset at temperatures at or above 0 c. ? black level correction ? row noise correction ? column correction ? test patterns several test patterns may be enabled for debug purposes. these include a solid color, color bar, fade to grey, and a walking 1s test pattern. pixel data format pixel array structure the ar0135cs pixel array is configured as 1412 columns by 1028 rows, (see figure 2). the dark pixels are optically black and are used internally to monitor black level. of the right 108 columns, 64 are dark pixels used for row noise correction. of the top 24 rows of pixels, 12 of the dark rows are used for black level correction. there are 1288 columns by 972 rows of optically active pixels that can be readable. while the sensor?s format is 1280 960, the additional active columns and active rows are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. the active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. not all dummy pixels or barrier pixels can be read out. the optical center of the readable active pixels can be found between x_addr 643 and 644, and between y_addr 485 and 486. figure 2. pixel array description 1412 1028 dark pixel barrier pixel light dummy pixel readable active pixel extra active pixel 4 extra active + 2 light dummy + 4 barrier + 24 dark + 10 barrier 1288 972 (readable active pixel) 4.83 3.645 mm 2 2 extra active + 2 light dummy + 4 barrier + 100 dark + 4 barrier 6 extra active + 2 light dummy + 4 barrier 2 light dummy + 10 barrier
ar0135cs www.onsemi.com 5 figure 3. pixel mono pattern detail (top right corner) c c c c c c column readout direction row readout direction active pixel (0, 0) array pixel (112, 44) c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c figure 4. pixel color pattern detail (top right corner) g b g b g b r g r g r g r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b column readout direction row readout direction active pixel (0, 0) array pixel (112, 44) default readout order by convention, the sensor core pixel array is shown with the first addressable (logical) pixel (0,0) in the top right corner (see figure 3). this reflects the actual layout of the array on the die. also, the physical location of the first pixel data read out of the sensor in default condition is that of pixel (112, 44).
ar0135cs www.onsemi.com 6 configuration and pinout the figures and tables below show a typical configuration for the ar0135cs image sensor and show the package pinouts. figure 5. serial 4-lane hispi interface 1. all power supplies must be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5 k , but a greater value may be used for slower two-wire speed. 3. this pull-up resistor is not required if the controller drives a valid logic level on s clk at all times. 4. the parallel interface output pads can be left unconnected if the serial output interface is used. 5. on semiconductor recommends that 0.1 f and 10 f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on the layout and design considerations. refer to the ar0135cs demo headboard schematics for circuit recommendations. 6. on semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes i s minimized. 7. although 4 serial lanes are shown, the ar0135cs supports only 2- or 3-lane hispi. notes: flash slvs0_p slvs0_n slvs1_p slvs1_n slvs2_p slvs2_n v dd _pll v dd _io v aa v aa _pix a gnd d gnd v aa _pix v aa v dd _io v dd s data s clk extclk 1.5 k 2 1.5 k 2, 3 oe_bar reset_bar test to controller from controller master clock (6?50 mhz) digital i/o power 1 digital core power 1 analog power 1 analog power 1 analog ground digital ground standby v dd _slvs hispi power 1 v dd _pll pll power 1 slvs3_p slvs3_n slvsc_p slvsc_n v dd v dd _slvs
ar0135cs www.onsemi.com 7 figure 6. parallel pixel data interface 1. all power supplies must be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5 k , but a greater value may be used for slower two-wire speed. 3. this pull-up resistor is not required if the controller drives a valid logic level on s clk at all times. 4. the serial interface output pads can be left unconnected if the parallel output interface is used. 5. on semiconductor recommends that 0.1 f and 10 f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on the layout and design considerations. refer to the ar0135cs demo headboard schematics for circuit recommendations. 6. on semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes i s minimized. notes: frame_valid line_valid pixclk flash v dd _io v dd v aa v aa _pix a gnd d gnd v aa _pix v aa v dd _io v dd extclk s data s clk 1.5 k 2 1.5 k 2, 3 trigger oe_bar reset_bar test to controller from controller master clock (6?50 mhz) digital i/o power 1 digital core power 1 analog power 1 analog power 1 analog ground digital ground d out [11:0] standby pll power 1 v dd _pll v dd _pll
ar0135cs www.onsemi.com 8 figure 7. 9 9 mm 60-ball ibga package top view (ball down) a b c d e f g h 12345678 v dd _pll extclk s addr line_ valid d out 8 d out 4 d out 0 slvscn v dd _slvs s clk frame_ valid d out 9 d out 5 d out 1 slvs0n slvscp (slvs3n) s data pixclk d out 10 d out 6 d out 2 slvs0p slvs2n (slvs3p) d gnd flash d out 11 d out 7 d out 3 slvs1n slvs2p d gnd d gnd d gnd d gnd d gnd d gnd slvs1p v dd v dd v dd v dd _io v dd _io v dd _io v dd _io v dd v aa a gnd v aa _pix reserved test trigger v dd _io v dd v aa a gnd v aa _pix reserved reserved oe_bar reset_ bar standby table 3. pin descriptions ? 63-ball ibga package name ibga pin type description slvs0_n a2 output hispi serial data, lane 0, differential n slvs0_p a3 output hispi serial data, lane 0, differential p slvs1_n a4 output hispi serial data, lane 1, differential n slvs1_p a5 output hispi serial data, lane 1, differential p standby a8 input standby-mode enable pin (active high) vdd_pll b1 power pll power slvsc_n b2 output hispi serial ddr clock differential n
ar0135cs www.onsemi.com 9 table 3. pin descriptions ? 63-ball ibga package (continued) name description type ibga pin slvsc_p b3 output hispi serial ddr clock differential p slvs2_n b4 output hispi serial data, lane 2, differential n slvs2_p b5 output hispi serial data, lane 2, differential p v aa b7, b8 power analog power extclk c1 input external input clock v dd _slvs c2 power hispi power (may leave unconnected if parallel interface is used) slvs3_n c3 output (unsupported) hispi serial data, lane 3, differential n slvs3_p c4 output (unsupported) hispi serial data, lane 3, differential p d gnd c5, d4, d5, e5, f5, g5, h5 power digital gnd v dd a6, a7, b6, c6, d6 power digital power a gnd c7, c8 power analog gnd s addr d1 input two-wire serial address select s clk d2 input two-wire serial clock input s data d3 i/o two-wire serial data i/o v aa _pix d7, d8 power pixel power line_valid e1 output asserted when d out line data is valid frame_valid e2 output asserted when d out frame data is valid pixclk e3 output pixel clock out. d out is valid on rising edge of this clock flash e4 output control signal to drive external light sources v dd _io e6, f6, g6, h6, h7 power i/o supply power d out 8 f1 output parallel pixel data output d out 9 f2 output parallel pixel data output d out 10 f3 output parallel pixel data output d out 11 f4 output parallel pixel data output (msb) test f7 input manufacturing test enable pin (connect to d gnd ) d out 4 g1 output parallel pixel data output d out 5 g2 output parallel pixel data output d out 6 g3 output parallel pixel data output d out 7 g4 output parallel pixel data output trigger g7 input exposure synchronization input. (connect to d gnd if hispi interface is used) oe_bar g8 input output enable (active low) d out 0 h1 output parallel pixel data output (lsb) d out 1 h2 output parallel pixel data output d out 2 h3 output parallel pixel data output d out 3 h4 output parallel pixel data output reset_bar h8 input asynchronous reset (active low). all settings are restored to factory default reserved e7, e8, f8 n/a reserved (do not connect)
ar0135cs www.onsemi.com 10 two-wire serial register interface the two-wire serial interface bus enables read/write access to control and status registers within the ar0135cs. the interface protocol uses a master/slave model in which a master controls one or more slave devices. the sensor acts as a slave device. the master generates a clock (s clk ) that is an input to the sensor and is used to synchronize transfers. data is transferred between the master and the slave on a bidirectional signal (s data ). s data is pulled up to v dd _ io off-chip by a 1.5 k resistor. either the slave or master device can drive s data low ? the interface protocol determines which device is allowed to drive s data at any given time. the protocols described in the two-wire serial interface specification allow the slave device to drive s clk low; the ar0135cs uses s clk as an input only and therefore never drives it low. protocol data transfers on the two-wire serial interface bus are performed by a sequence of low-level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition the bus is idle when both s clk and s data are high. control of the bus is initiated with a start condition, and the bus is released with a stop condition. only the master can generate the start and stop conditions. start condition a start condition is defined as a high-to-low transition on s data while s clk is high. at the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a ?repeated start? or ?restart? condition. stop condition a stop condition is defined as a low -to-high transition on s data while s clk is high. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for the slave address/data direction byte and for message bytes. one data bit is transferred during each s clk clock period. s data can change when s clk is low and must be stable while s clk is high. slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the default slave addresses used by the ar0135cs are 0x20 (write address) and 0x21 (read address) in accordance with the specification. alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the s addr input. an alternate slave address can also be programmed through r0x31fc. message byte message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the s clk clock period following the data transfer. the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowledge bit by driving s data low. as for data transfers, s data can change when s clk is low and must be stable while s clk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the s clk clock period following a data transfer. a no-acknowledge bit is used to terminate a read sequence. typical sequence a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indicates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. if the request was a write, the master then transfers the 16-bit register address to which the write should take place. this transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. the master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. the master stops writing by generating a (re)start or stop condition. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. the master generates an acknowledge bit after each 8-bit transfer. the slave?s internal register address is automatically incremented after every 8 bits are transferred. the data transfer is stopped when the master sends a no-acknowledge bit.
ar0135cs www.onsemi.com 11 single read from random location this sequence (figure 8) starts with a dummy write to the 16-bit address that is to be used for the read. the master terminates the write by generating a restart condition. the master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. the master terminates the read by generating a no-acknowledge bit followed by a stop condition. figure 8 show s how the internal register address maintained by the ar0135cs is loaded and incremented as the sequence proceeds. figure 8. single read from random location previous reg address, n reg address, m m+1 s0 1 p a sr slave address reg address[15:8] reg address[7:0] slave address s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave a a a a read data single read from current location this sequence (figure 9) performs a read using the current value of the ar0135cs internal register address. the master terminates the read by generating a no-acknowledge bit followed by a stop condition. the figure shows two independent read sequences. figure 9. single read from current location previous reg address, n reg address, n+1 n+2 s1 p slave address aa read data s1 p slave address aa read data sequential read, start from random location this sequence (figure 10) starts in the same way as the single read from random location (figure 8). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 10. sequential read, start from random location previous reg address, n reg address, m s0 slave address a a reg address[15:8] p a m+1 a a a 1 sr reg address[7:0] read data slave address m+l m+l?1 m+l?2 m+1 m+2 m+3 a read data a read data a read data read data
ar0135cs www.onsemi.com 12 sequential read, start from current location this sequence (figure 11) starts in the same way as the single read from current location (figure 9). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 11. sequential read, start from current location n+l n+l?1 n+2 n+1 previous reg address, n p a s 1 read data a slave address read data read data read data aaa single write to random location this sequence (figure 12) begins with the master generating a start condition. the slave address/data direction byte signals a write and is followed by the high then low bytes of the register address that is to be written. the master follows this with the byte of write data. the write is terminated by the master generating a stop condition. figure 12. single write to random location previous reg address, n reg address, m m+1 s0 p slave address reg address[15:8] reg address[7:0] a a a a a write data sequential write, start at random location this sequence (figure 13) starts in the same way as the single write to random location (figure 12). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until ?l? bytes have been written. the write is terminated by the master generating a stop condition. figure 13. sequential write, start at random location previous reg address, n reg address, m m+1 s0 slave address a reg address[15:8] a a a reg address[7:0] write data m+l m+l?1 m+l?2 m+1 m+2 m+3 write data a a a ap a write data write data write data
ar0135cs www.onsemi.com 13 electrical specifications unless otherwise stated, the following specifications apply to the following conditions: v dd = 1.8 v ?0.10/+0.15; v dd _io = v dd _pll = v aa = v aa _pix = 2.8 v 0.30; v dd _slvs = 0.4 v ?0.1/+0.2; t a = ?30 c to +70 c; output load = 10 pf; pixclk frequency = 74.25 mhz; hispi off. two-wire serial register interface the electrical characteristics of the two-wire serial register interface (s clk , s data ) are shown in figure 14 and table 4. figure 14. two-wire serial bus timing parameters s data s clk s sr p s t f t r t f t r t su;dat t hd;sta t su;sto t su;sta t buf t hd;dat t high t low t hd;sta note: read sequence: for an 8-bit read, read waveforms start after write command and register address are issued. table 4. two-wire serial bus characteristics (f extclk = 27 mhz; v dd = 1.8 v; v dd _io = 2.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; v dd _dac = 2.8 v; t a = 25 c) parameter symbol standard mode fast-mode unit min max min max s clk clock frequency t scl 0 100 0 400 khz hold time (repeated) start condition after this period, the first clock pulse is generated t hd;sta 4.0 ? 0.6 ? s low period of the s clk clock t low 4.7 ? 1.3 ? s high period of the s clk clock t high 4.0 ? 0.6 ? s set-up time for a repeated start condition t su;sta 4.7 ? 0.6 ? s data hold time t hd;dat 0 (note 4) 3.45 (note 5) 0 (note 6) 0.9 (note 5) s data set-up time t su;dat 250 ? 100 (note 6) ? ns rise time of both s data and s clk signals t r ? 1000 20 + 0.1cb (note 7) 300 ns fall time of both s data and s clk signals t f ? 300 20 + 0.1cb (note 7) 300 ns set-up time for stop condition t su;sto 4.0 ? 0.6 ? s bus free time between a stop and start condition t buf 4.7 ? 1.3 ? s capacitive load for each bus line cb ? 400 ? 400 pf serial interface input pin capacitance cin_si ? 3.3 ? 3.3 pf
ar0135cs www.onsemi.com 14 table 4. two-wire serial bus characteristics (continued) (f extclk = 27 mhz; v dd = 1.8 v; v dd _io = 2.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; v dd _dac = 2.8 v; t a = 25 c) parameter unit fast-mode standard mode symbol parameter unit max min max min symbol s data max load capacitance cload_sd ? 30 ? 30 pf s data pull-up resistor rsd 1.5 4.7 1.5 4.7 k 1. this table is based on i 2 c standard (v2.1 january 2000). philips semiconductor. 2. two-wire control is i 2 c-compatible. 3. all values referred to v ihmin = 0.9 v dd _io and v ilmax = 0.1 v dd _io levels. sensor exclk = 27 mhz. 4. a device must internally provide a hold time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk . 5. the maximum t hd;dat has only to be met if the device does not stretch the low period (t low ) of the s clk signal. 6. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the s clk signal. if such a device does stretch the low period of the s clk signal, it must output the next data bit to the s data line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the s clk line is released. 7. cb = total capacitance of one bus line in pf. i/o timing by default, the ar0135cs launches pixel data, fv and lv with the falling edge of pixclk. the expectation is that the user captures d out [11:0], fv and lv using the rising edge of pixclk. the launch edge of pixclk can be configured in register r0x3028. see figure 15 and table 5 for i/o timing (ac) characteristics. figure 15. i/o timing diagram extclk pixclk data[11:0] line_valid/ frame_valid pxl_0 pxl_1 pxl_2 pxl_n t pf l t pl l t fp t rp t f t r 90% 90% 90% 90% 10% 10% 10% 10% t extclk t pd t plh t pfh frame_valid leads line_valid by 6 pixclks frame_valid trails line_valid by 6 pixclks table 5. i/o timing characteristics, parallel output (1.8 v v dd _io) (note 1) symbol definition condition min typ max unit f extclk input clock frequency 6 ? 50 mhz t extclk input clock period 20 ? 166 ns t r input clock rise time pll enabled ? 3 ? ns t f input clock fall time pll enabled ? 3 ? ns t j jitter input clock jitter ? ? 600 ns t cp extclk to pixclk propagation delay nominal voltages, pll disabled, pixclk slew rate = 4 5.7 ? 14.3 ns t rp pixclk rise time pclk slew rate = 6 1.3 ? 4.0 ns t fp pixclk fall time pclk slew rate = 6 1.3 ? 3.9 ns pixclk duty cycle 40 50 60 % f pixclk pixclk frequency pixclk slew rate = 6, data slew rate = 7 6 ? 74.25 mhz t pd pixclk to data valid pixclk slew rate = 6, data slew rate = 7 ?2.5 ? 2 ns
ar0135cs www.onsemi.com 15 table 5. i/o timing characteristics, parallel output (1.8 v v dd _io) (note 1) (continued) symbol unit max typ min condition definition t pfh pixclk to fv high pixclk slew rate = 6, data slew rate = 7 ?2.5 ? 2 ns t plh pixclk to lv high pixclk slew rate = 6, data slew rate = 7 ?3 ? 1.5 ns t pfl pixclk to fv low pixclk slew rate = 6, data slew rate = 7 ?2.5 ? 2 ns t pll pixclk to lv low pixclk slew rate = 6, data slew rate = 7 ?3 ? 1.5 ns c in input pin capacitance ? 2.5 ? pf 1. minimum and maximum values are taken at 70 c, 1.7 v and ?30 c, 1.95 v. all values are taken at the 50% transition point. the loading used is 10 pf. 2. jitter from pixclk is already taken into account in the data for all of the output parameters. table 6. i/o timing characteristics, parallel output (2.8 v v dd _io) (note 1) symbol definition condition min typ max unit f extclk input clock frequency 6 ? 50 mhz t extclk input clock period 20 ? 166 ns t r input clock rise time pll enabled ? 3 ? ns t f input clock fall time pll enabled ? 3 ? ns t j jitter input clock jitter ? ? 600 ns t cp extclk to pixclk propagation delay nominal voltages, pll disabled, pixclk slew rate = 4 5.3 ? 13.4 ns t rp pixclk rise time pclk slew rate = 6 1.3 ? 4.0 ns t fp pixclk fall time pclk slew rate = 6 1.3 ? 3.9 ns pixclk duty cycle 40 50 60 % f pixclk pixclk frequency pixclk slew rate = 6, data slew rate = 7 6 ? 74.25 mhz t pd pixclk to data valid pixclk slew rate = 6, data slew rate = 7 ?2.5 ? 2 ns t pfh pixclk to fv high pixclk slew rate = 6, data slew rate = 7 ?2.5 ? 2 ns t plh pixclk to lv high pixclk slew rate = 6, data slew rate = 7 ?2.5 ? 2 ns t pfl pixclk to fv low pixclk slew rate = 6, data slew rate = 7 ?2.5 ? 2 ns t pll pixclk to lv low pixclk slew rate = 6, data slew rate = 7 ?2.5 ? 2 ns c in input pin capacitance ? 2.5 ? pf 1. minimum and maximum values are taken at 70 c, 2.5 v and ?30 c, 3.1 v. all values are taken at the 50% transition point. the loading used is 10 pf. 2. jitter from pixclk is already taken into account in the data for all of the output parameters. table 7. i/o rise slew rate (2.8 v v dd _io) (note 1) parallel slew (r0x306e[15:13]) condition min typ max unit 7 default 1.50 2.50 3.90 v/ns 6 default 0.98 1.62 2.52 v/ns 5 default 0.71 1.12 1.79 v/ns 4 default 0.52 0.82 1.26 v/ns 3 default 0.37 0.58 0.88 v/ns 2 default 0.26 0.40 0.61 v/ns 1 default 0.17 0.27 0.40 v/ns 0 default 0.10 0.16 0.23 v/ns 1. minimum and maximum values are taken at 70 c, 2.5 v and ?30 c, 3.1 v. the loading used is 10 pf.
ar0135cs www.onsemi.com 16 table 8. i/o fall slew rate (2.8 v v dd _io) (note 1) parallel slew (r0x306e[15:13]) condition min typ max unit 7 default 1.40 2.30 3.50 v/ns 6 default 0.97 1.61 2.48 v/ns 5 default 0.73 1.21 1.86 v/ns 4 default 0.54 0.88 1.36 v/ns 3 default 0.39 0.63 0.88 v/ns 2 default 0.27 0.43 0.66 v/ns 1 default 0.18 0.29 0.44 v/ns 0 default 0.11 0.17 0.25 v/ns 1. minimum and maximum values are taken at 70 c, 2.5 v and ?30 c, 3.1 v. the loading used is 10 pf. table 9. i/o rise slew rate (1.8 v v dd _io) (note 1) parallel slew (r0x306e[15:13]) condition min typ max unit 7 default 0.57 0.91 1.55 v/ns 6 default 0.39 0.61 1.02 v/ns 5 default 0.29 0.46 0.75 v/ns 4 default 0.22 0.34 0.54 v/ns 3 default 0.16 0.24 0.39 v/ns 2 default 0.12 0.17 0.27 v/ns 1 default 0.08 0.11 0.18 v/ns 0 default 0.05 0.07 0.10 v/ns 1. minimum and maximum values are taken at 70 c, 1.7 v and ?30 c, 1.95 v. the loading used is 10 pf. table 10. i/o fall slew rate (1.8 v v dd _io) (note 1) parallel slew (r0x306e[15:13]) condition min typ max unit 7 default 0.57 0.92 1.55 v/ns 6 default 0.40 0.64 1.08 v/ns 5 default 0.31 0.50 0.82 v/ns 4 default 0.24 0.38 0.61 v/ns 3 default 0.18 0.27 0.44 v/ns 2 default 0.13 0.19 0.31 v/ns 1 default 0.09 0.13 0.20 v/ns 0 default 0.05 0.08 0.12 v/ns 1. minimum and maximum values are taken at 70 c, 1.7 v and ?30 c, 1.95 v. the loading used is 10 pf.
ar0135cs www.onsemi.com 17 dc electrical characteristics the dc electrical characteristics are shown in table 11, table 12, table 13, table 14, and table 15. table 11. dc electrical characteristics symbol definition condition min typ max unit v dd core digital voltage 1.7 1.8 1.95 v v dd _ io i/o digital voltage 1.7/2.5 1.8/2.8 1.9/3.1 v v aa analog voltage 2.5 2.8 3.1 v v aa _pix pixel supply voltage 2.5 2.8 3.1 v v dd _ pll pll supply voltage 2.5 2.8 3.1 v v dd _slvs hispi supply voltage 0.3 0.4 0.6 v v ih input high voltage v dd _ io 0.7 ? ? v v il input low voltage ? ? v dd _ io 0.3 v i in input leakage current no pull-up resistor; v in = v dd _ io or d gnd 20 ? ? a v oh output high voltage v dd _ io ? 0.3 ? ? v v ol output low voltage v dd _ io = 2.8 v ? ? 0.4 v i oh output high current at specified v oh ?22 ? ? ma i ol output low current at specified v ol ? ? 22 ma caution: stresses greater than those listed in table 12 may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. table 12. absolute maximum ratings symbol parameter minimum maximum unit v supply power supply voltage (all supplies) ?0.3 4.5 v i supply total power supply current ? 200 ma i gnd total ground current ? 200 ma v in dc input voltage ?0.3 v dd _ io + 0.3 v v out dc output voltage ?0.3 v dd _ io + 0.3 v t stg (note 1) storage temperature ?40 +85 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 13. operating current consumption for parallel output (v aa = v aa _pix = v dd _io = v dd _pll = 2.8 v; v dd = 1.8 v; pll enabled and pixclk = 74.25 mhz; t a = 25 c; c load = 10 pf) symbol parameter condition min typ max unit i dd digital operating current parallel, streaming, full resolution 54 fps ? 46 60 ma i dd _io i/o digital operating current parallel, streaming, full resolution 54 fps ? 52 ? ma i aa analog operating current parallel, streaming, full resolution 54 fps ? 46 55 ma i aa _pix pixel supply current parallel, streaming, full resolution 54 fps ? 7 9 ma i dd _pll pll supply current parallel, streaming, full resolution 54 fps ? 8 10 ma
ar0135cs www.onsemi.com 18 table 14. operating current consumption for hispi output (v aa = v aa _pix = v dd _io = v dd _pll = 2.8 v; v dd = 1.8 v; pll enabled and pixclk = 74.25 mhz; t a = 25 c; c load = 10 pf) symbol parameter condition min typ max unit i dd digital operating current hispi, streaming, full resolution 54 fps ? 70 90 ma i dd _io i/o digital operating current hispi, streaming, full resolution 54 fps ? 0.2 1 ma i aa analog operating current hispi, streaming, full resolution 54 fps ? 40 55 ma i aa _pix pixel supply current hispi, streaming, full resolution 54 fps ? 7 9 ma i dd _pll pll supply current hispi, streaming, full resolution 54 fps ? 11 14 ma i dd _slvs hispi supply current hispi, streaming, full resolution 54 fps ? 9 12 ma table 15. standby current consumption (analog ? v aa + v aa _pix + v dd _pll; digital ? v dd + v dd _io; t a = 25 c) definition condition min typ max unit hard standby (clock off, driven low) analog, 2.8 v ? 3 15 a digital, 1.8 v ? 25 125 a hard standby (clock on, extclk = 20 mhz) analog, 2.8 v ? 12 25 a digital, 1.8 v ? 1.1 1.7 ma soft standby (clock off, driven low) analog, 2.8 v ? 3 15 a digital, 1.8 v ? 25 125 a soft standby (clock on, extclk = 20 mhz) analog, 2.8 v ? 12 25 a digital, 1.8 v ? 1.1 1.7 ma hispi electrical specifications the on semiconductor ar0135cs sensor supports slvs mode only, and does not have a dll for timing adjustments. refer to the high-speed serial pixel (hispi) interface physical layer specification v2.00.00 for electrical definitions, specifications, and timing information. the v dd _slvs supply in this data sheet corresponds to v dd _tx in the hispi physical layer specification. similarly, v dd is equivalent to v dd _hispi as referenced in the specification. the hispi transmitter electrical specifications are listed at 700 mhz. table 16. input voltage and current (hispi power supply 0.4 v) (measurement conditions: max freq. 700 mhz) symbol parameter min typ max unit i dd _slvs supply current (pwr hispi ) (driving 100 load) ? 10 15 ma v cmd hispi common mode voltage (driving 100 load) v dd _ slvs 0.45 v dd _slvs/2 v dd _ slvs 0.55 v |v od | hispi differential output voltage (driving 100 load) v dd _ slvs 0.36 v dd _slvs/2 v dd _ slvs 0.64 v v cm change in v cm between logic 1 and 0 ? ? 25 mv |v od | change in |v od | between logic 1 and 0 ? ? 25 mv nm v od noise margin ? ? 30 % | v cm | difference in v cm between any two channels ? ? 50 mv | v od | difference in v od between any two channels ? ? 100 mv v cm_ac common-mode ac voltage (pk) without v cm cap termination ? ? 50 mv v cm_ac common-mode ac voltage (pk) with v cm cap termination ? ? 30 mv v od_ac max overshoot peak |v od | ? ? 1.3 |v od | v v diff_pkpk max overshoot v diff pk-pk ? ? 2.6 |v od | v v eye eye height 1.4 v od ? ? r o single-ended output impedance 35 50 70 r o output impedance mismatch ? ? 20 %
ar0135cs www.onsemi.com 19 figure 16. differential output voltage for clock and data pairs v diffmin v diffmax 0 v (diff) output signal is ?cp ? cn? or ?dp ? dn? table 17. rise and fall times (measurement conditions: hispi power supply 0.4 v, max freq. 700 mhz) symbol parameter min typ max unit 1/ui data rate 280 ? 700 mb/s txpre max setup time from transmitter 0.3 ? ? ui (note 1) txpost max hold time from transmitter 0.3 ? ? ui rise rise time (20%?80%) ? 0.25 ui ? fall fall time (20%?80%) 150ps 0.25 ui ? pll_duty clock duty 45 50 55 % t pw bitrate period 1.43 ? 3.57 ns (note 1) t eye eye width 0.3 ? ? ui (notes 1, 2) t totaljit data total jitter (pk pk)@1e?9 ? ? 0.2 ui (notes 1, 2) t ckjit clock period jitter (rms) ? ? 50 ps (note 2) t cyjit clock cycle-to-cycle jitter (rms) ? ? 100 ps (note 2) t chskew clock to data skew ?0.1 ? 0.1 ui (notes 1, 2) t |physkew| phy-to-phy skew ? ? 2.1 ui (notes 1, 5) t diffskew mean differential skew ?100 ? 100 ps (note 6) 1. one ui is defined as the normalized mean time between one edge and the following edge of the clock. 2. taken from 0 v crossing point. 3. also defined with a maximum loading capacitance of 10 pf on any pin. the loading capacitance may also need to be less for higher bitr ates so the rise and fall times do not exceed the maximum 0.3 ui. 4. the absolute mean skew between the clock lane and any data lane in the same phy between any edges. 5. the absolute mean skew between any clock in one phy and any data lane in any other phy between any edges. 6. differential skew is defined as the skew between complementary outputs. it is measured as the absolute time between the two complementary edges at mean v cm point.
ar0135cs www.onsemi.com 20 figure 17. eye diagram for clock and data signals data mask clock mask trigger/reference ui/2 ui/2 rise fall v diff max v diff txpre txpost 80% 20% v diff clkjitter figure 18. skew within the phy and output channels vcmd t cmpskew t chskew1phy
ar0135cs www.onsemi.com 21 power-on reset and standby timing power-up sequence the recommended power-up sequence for the ar0135cs is shown in figure 19. the available power supplies (v dd _ io, v dd , v dd _ slvs , v dd _pll, v aa , v aa _ pix) must have the separation specified below. 1. turn on v dd _ pll power supply. 2. after 0?10 s, turn on v aa and v aa _ pix power supply. 3. after 0?10 s, turn on v dd _io power supply. 4. after the last power supply is stable, enable extclk. 5. if reset_bar is in a low state, hold reset_bar low for at least 1 ms. if reset_bar is in a high state, assert reset_bar for at least 1 ms. 6. wait 160000 extclks (for internal initialization into software standby). 7. configure pll, output, and image settings to desired values. 8. wait 1 ms for the pll to lock. 9. set streaming mode (r0x301a[2] = 1). figure 19. power up extclk v dd _slvs (0.4) v aa _pix v aa (2.8) v dd _io (1.8/2.8) v dd (1.8) v dd _pll (2.8) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t x hard reset internal initialization software standby pll clock streaming reset_bar table 18. power-up sequence symbol definition min typ max unit t 0 v dd _pll to v aa /v aa _pix 0 10 ? s t 1 v aa /v aa _pix to v dd _io 0 10 ? s t 2 v dd _io to v dd 0 10 ? s t 3 v dd to v dd _slvs 0 10 ? s t x xtal settle time ? 30 (note 1) ? ms t 4 hard reset 1 (note 2) ? ? ms t 5 internal initialization 160000 ? ? extclks t 6 pll lock time 1 ? ? ms 1. xtal settling time is component-dependent, usually taking about 10?100 ms. 2. hard reset time is the minimum time required after power rails are settled. in a circuit where hard reset is held down by rc circuit, then the rc time must include the all power rail settle time and xtal settle time. 3. it is critical that v dd _pll is not powered up after the other power supplies. it must be powered before or at least at the same time as the others. if the case happens that v dd _pll is powered after other supplies then the sensor may have functionality issues and will experience high current draw on this supply.
ar0135cs www.onsemi.com 22 power-down sequence the recommended power-down sequence for the ar0135cs is shown in figure 20. the available power supplies (v dd _ io, v dd , v dd _ slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. disable streaming if output is active by setting standby r0x301a[2] = 0 2. the soft standby state is reached after the current row or frame, depending on configuration, has ended. 3. turn off v dd _slvs. 4. turn off v dd . 5. turn off v dd _io 6. turn off v aa /v aa _pix. 7. turn off v dd _pll. figure 20. power down extclk v dd _pll (2.8) v dd _io (1.8/2.8) v dd (1.8) v dd _slvs (0.4) t 0 power down until next power up cycle t 1 t 2 t 3 t 4 v aa _pix v aa (2.8) table 19. power-down sequence symbol parameter min typ max unit t 0 v dd _slvs to v dd 0 ? ? s t 1 v dd to v dd _io 0 ? ? s t 2 v dd _io to v aa /v aa _pix 0 ? ? s t 3 v aa /v aa _pix to v dd _pll 0 ? ? s t 4 pwrdn until next pwrup time 100 ? ? ms 1. t 4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.
ar0135cs www.onsemi.com 23 standby sequence figure 21 and figure 22 show timing diagrams for entering and exiting standby. delays are shown indicating the last valid register write prior to entering standby as well as the first valid write upon exiting standby. also shown is timing if the extclk is to be disabled during standby. figure 21. enter standby timing extclk standby fv sdata register writes not valid register writes valid 750 extclks 50 extclks figure 22. exit standby timing extclk standby fv trigger sdata register writes not valid register writes valid 1ms 10 extclks 28 rows + cit
ar0135cs www.onsemi.com 24 figure 23. quantum efficiency ? monochrome sensor (typical) 0 10 20 30 40 50 60 70 80 350 450 550 650 750 850 950 1050 quantum efficiency (%) wavelength (nm) 400 500 600 700 800 900 1000 1100 figure 24. quantum efficiency ? color sensor (typical) 0 10 20 30 40 50 60 70 350 450 550 650 750 850 950 1050 quantum efficiency (%) wavelength (nm) red green blue
ar0135cs www.onsemi.com 25 cra vs. image height plot image height cra (%) (mm) (deg) chief ray angle (degrees) image height (%) ar1335cs cra characteristic 0 10 2030 40506070 8090100110 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 0 0 5 0.150 1.35 10 0.300 2.70 15 0.450 4.04 20 0.600 5.39 25 0.750 6.73 30 0.900 8.06 35 1.050 9.39 40 1.200 10.71 45 1.350 12.02 50 1.500 13.33 55 1.650 14.62 60 1.800 15.90 65 1.950 17.16 70 2.100 18.41 75 2.250 19.64 80 2.400 20.85 85 2.550 22.05 90 2.700 23.22 95 2.850 24.38 100 3.000 25.51 figure 25. chief ray angle ? 25
ar0135cs www.onsemi.com 26 package dimensions ibga63 9x9 case 503az issue o notes: 1. lid material: borosilicate glass 0.4 0.04 thickness. refractive index at 20 c = 1.5255 @ 546 nm and 1.5231 @ 588 nm. double side ar coating: 530?570 nm r < 1%; 420?700 nm r < 2%. 2. solder ball material: sac305 (95% sn, 3% ag, 0.5% cu). dimensions apply to solder balls post reflow. pre-flow ball is 0.5 on a ? 0.4 smd ball pad.
ar0135cs www.onsemi.com 27 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ar0135cs/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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